Interrupts

Originally, hardware interrupts were introduced as an optimisation, which eliminate unproductive waiting time in polling loops whilst waiting for external events.

Polling loops: Polling refers to actively sampling the status of an external device by a client program as a synchronous activity.

The first system to use this type of approach was in 1954 and was referred to as DYSEAC, which was built by the National Bureau of Standards for the US Army.

(This was implemented on a truck, hence probably making it one of the first movable computers)

Although the first system to use interrupts was the UNIVAC 1103 computer in 1953, which was an American made computer.

What are Interrupts?

Interrupts are a response by the processor to a process/event that needs immediate attention from the software.

Interrupts alert the processor and servers a a request for the CPU to interrupt the currently executing program/code when permitted, in order so that the event can be processed within good time.

If the response is accepted from the processor, the processor will respond by suspending its current activities (saving its state), and thus executing a function called an interrupt handler to deal with the event.

This interrupt in activities and programs is only temporary, that is, unless the interrupt indicates a fatal error, otherwise the processor will resume all normal running actives after the interrupt handler finishes.

Interrupts are used by both hardware and software to indicate electric or physical state changes that require attention.

Interrupts have a heavy usage in computer multi-tasking, especially in real-time computing, moreover, these systems that utilise interrupts are said to be “interrupt-driven”.

One of the advantages of interrupts is that they can be used to break an infinite loop, which can create memory leaks or cause a program to be unresponsive.

What is an Interrupt handler?

Interrupt handlers, also commonly known as Interrupt service routine (ISR), is a block of code that is associated with a specific interrupt condition.

Hardware and software interrupts or software exceptions initiate the interrupt handler, furthermore the interrupt handler is used to implement device drivers or transitions between protected modes of operation, such as system calls.

Interrupts have a number of functions, which ultimately depend on what triggered the interrupt in the first place, therefore the speed of which an interrupt handler completes its tasks also varies depending on what triggered the interrupt.

For instance, moving the mouse or pressing a key on the keyboard, will trigger interrupt handlers which read they key, or the position of the mouse, lastly the interrupt handlers will copy the information associated with those actions into the computers memory.

There are two types of interrupt handlers: First Level Interrupt handler (FLIH), and Second Level Interrupt Handler (SLIH).

Jitter: Jitter refers to small intermittent delays during data transfers. It can be caused by a number of different factors, such as collisions, signal interference, and network congestion etc.

First Level Interrupt handler (FLIH):

This type of interrupt handler is the faster of the two, it also has more jitter while process is getting executed and they are mainly maskable interrupts.

The functionality of FLIH is to quickly service the interrupt, or to record platform specific critical information (that is only available at the time of the interrupt) and then schedule SLIH execution for further (more slowly) interrupt handling.

In order to reduce jitter and hence the possibility of losing data from masked interrupts in such operating systems (like real time operating systems), programmers attempt to reduce the execution time of FLIH, attempting to move as much functionality as they can to SLIH.

Ultimately, with our fast processing computer systems, FLIH will implement all device and platform dependent handling, and then use SLIH for further platform independent long term handling.

Second Level Interrupt Handler (SLIH):

The functionality of SLIH is they complete long interrupt processing tasks, just like processes. SLIHs either have a kernel thread which is dedicated for each handler, or are executed by a pool of kernel worker threads. Just like processes, these handlers sit on a run queue in the operating system until the processor time is available for them to perform processing for the interrupt.

SLIHs, unlike FLIH, can be scheduled similarly to processes and threads.

Types of Interrupts

Interrupts signals as mentioned above, are a response to software or hardware events in the system. These events are classified as software interrupts or hardware interrupts.

For any processor, the total number of interrupt types is limited by the architecture.

Hardware Interrupts:

All the devices are connected to the Interrupt Request Line (IRQ) or detected by devices embedded in processor logic (i.e. the CPU timer), to communicate that the certain device requires attention from the operating system, and if there is no operating system, then seek attention from “bare-metal” program which is running on the CPU.

Moving the mouse is considered to be using hardware interrupts.

Interrupt Request Line (IRQ): An IRQ refers to a hardware signal sent to the processor that temporarily stops a running program and allows the interrupt handler to run instead.

With regards to the processor clock, hardware interrupts can arrive asynchronously (transmission of data without the use of an external clock signal) with respect to the processor clock, and at any time during instruction execution.

That being said, all the hardware interrupt signals are conditioned by synchronising them to the processor clock, and acted upon only at instruction execution boundaries.

In many systems, the device that is causing the particular interrupt request can be identified, as each device is associated with a specific IRQ signal.

Masking:

Typically, processors have an internal interrupt mask register that allows selective enabling and disabling of hardware interrupts. Furthermore, each interrupt is linked with a bit in the mask register. In some systems, the interrupt is enabled when the bit is set and disabled when the bit is clear, while on other systems, the set bit disables the interrupt.

Therefore when the interrupt is disabled, the linked interrupt signal will be ignored by the processor.

In some cases, some interrupt signals cannot be affected by the interrupt mask, so they cannot be disabled, these are referred to be non-maskable interrupts.

Such types of interrupts have an extremely high priority and cannot be ignored under any circumstance.

Therefore:

• Maskable interrupt:
  • The hardware interrupts can be delayed when a high priority interrupt has occurred at the same time.
• Non-Maskable interrupt:
  • The hardware interrupts which cannot be delayed, and therefore require the processor to process them immediately.

Spurious Interrupts:

These types of interrupt are categorised to be invalid, short-duration signal on an interrupt input. These types of interrupts are caused by glitches that are a result of electrical interference, race conditions, or malfunctioning devices.

Race condition: A race condition refers to an undesirable situation that occurs when a device or system attempts to perform two or more operations at the same time, though these operations must be done in a proper sequence to get executed properly.

Software Interrupts:

Software interrupts refer to an interrupt which is requested by the processor to execute particular instructions or when certain conditions are met.

These interrupts can be intentionally produced by executing a special instruction which, by design, invokes an interrupt when compiled.

Furthermore, software interrupts can also be triggered unexpectedly, by the program execution errors. These are referred to as traps or exceptions. An incorrect division by zero is an example of this. Though the operating system will catch and handle these exceptions.

(You can relate this when coding, try and catch blocks, you specify a possibility of an error(s) and allow the system to handle the solution if that error happens.)

Periodic Interrupt:

Interrupts that occur at a fixed interval in timeline.

Aperiodic Interrupt:

Interrupts that cannot be predicted.

Synchronous Interrupt:

Interrupts that are dependent and in phase to the system clock.

Asynchronous Interrupt:

Interrupts that are independent to the system clock and are not in phase to it.

Interrupts handling more than one device

Usually in computer systems, more than one device can cause an interrupt request signal, therefore additional information is required to allow the processor to decide which device to be considered first.

Below are a number of different methods the processor uses to decide its selection:

Polling:

In polling, the first device which is encountered by the Interrupt Request Line (IRQ) is the device that is serviced first. Therefore the appropriate interrupt service routine (ISR) is called to service the device. This mechanism is similar to first come first serve. Although polling is simple to implement, a lot of time is wasted by interrogating the IRQ of all the devices.

Vectored Interrupts:

Vector interrupts identify themselves using a special code that it sends out over a computer bus to the processor. This technique enables the processor to identify the device that generated the interrupt.

The special code that is sent out can be the starting address of the ISR or even where the ISR is located in memory, and is called the interrupt vector.

Interrupt Nesting:

In this method input/output devices are organised according to a priority structure. This means that interrupt requests from a higher priority device is recognised where as request from a lower priority is not.

Daisy Chaining Priority:

This mechanism consists of a serial connection of all the devices, which generate an interrupt signal. This configuration is governed by the priority of all the devices connected. The device with the highest priority is placed first and so on.

Interrupt Triggering Methods

Interrupts are usually triggered by two ways, either by a logic signal level or an edge triggered signal.

Level sensitive inputs request at a continuous pace processor service, as long as a particular logic level is applied to the input.

On the other hand, edge sensitive input reacts to signal edges, which are a particular rising/falling edges that will cause a service request to be latched. At the end, the processor resets the latch when the interrupt handler executes the action.

Level Triggered Method:

Level triggered interrupts are requested by pausing the interrupt signal at its particular (either high or low) active logic level.

Level triggered interrupts are invoked by a device when they drive the signal to and hold it at the active level. Typically after the device has been serviced, it negates the signal when the processor commands it to do so.

The processor will recognise the interrupt request if the signal is asserted, as the processor samples the interrupt input signal during each instruction cycle.

Level triggered interrupts always allow the generation of an interrupt whenever the level of interrupt source is asserted.

Logic level: In digital circuits, a logic level is considered to be one of a finite number of states that a digital signal can inhabit. Usually these are represent by the voltage difference between the signal and ground.

Edge Triggered Method:

An edge trigged interrupt refers to an interrupt that is signaled by a level transition on the interrupt line, either by a falling edge or a rising edge.

If a device wants to signal an interrupt, it will have to drive a pulse onto the line and then release the line to its inactive state, if the pulse is too short to be detected by the polled input/output, then a special price of hardware will be required to detect it.

In Edge trigged interrupt, interrupts are generated if it can detect an asserting edge of the interrupt source. The edge may be detected when the interrupt source level changes, furthermore, it can be detected by the continuous sampling and detection of asserted levels when the previous sample was de-asserted.

Pulse: The term pulse in signal processing is defined to a rapid, transit change in the amplitude of a single from a baseline value to a higher or lower value, then followed by a rapid return the baseline value.

Interrupt operations and processes

Basic operations of interrupts include:

1. CPU issues a read command.
2. Whilst the CPU processes, the input/output module get the data from the peripheral.
3. Input/output request data.
4. The CPU will request the data,
5. Input/output transfers data.

The process that occurs when an interrupt is processed:

1. A device driver initiates an input/output request on behalf of the process.
2. The requested input/output is initiated as the driver signals the input/output controller for the proper device.
3. Device signals the input/output controller, which is ready to receive input, moreover, the output is complete or an error has been generated.
4. The CPU will receive the interrupt signal on the IRL, thus, then transferring control to the interrupter handler routine.
5. At this point, the interrupt handler will determine the cause of the interrupt and will perform any necessary processing, once that’s complete, it will execute a “return from” interrupt instruction.
6. The CPU will return to the execution state prior to the interrupt being singled.
7. The CPU continues processing until the cycle begins again.

Summary and Facts

What are Interrupts?

Interrupts are signals that are sent to the CPU by external devices such as input/output devices. Interrupts communicate over to the CPU that it needs to stop its current activities and execute the approbate part of the operating system.

Interrupts are an important part of the system as they provide the user better control over the computer, without interrupt, a user may have to wait for the application they wish to use until it has a higher priory over the CPU to be ran, therefore the use of interrupts allows the CPU to deal with the application required immediately.

What is an Interrupt handler:

Interrupt handlers, also commonly known as Interrupt service routine (ISR), is a block of code that is associated with a specific interrupt condition.

There are two types of interrupt handlers:

1. First Level Interrupt handler (FLIH)
2. Second Level Interrupt Handler (SLIH)

Types of Interrupts

• Interrupt Request Line (IRQ): An IRQ refers to a hardware signal sent to the processor that temporarily stops a running program and allows the interrupt handler to run instead.
• Interrupts signals, are a response to software or hardware events in the system. These events are classified as software interrupts or hardware interrupts.
• For any processor, the total number of interrupt types is limited by the architecture.
• Hardware Interrupts
• Masking
  • Maskable interrupt
  • Non-Maskable interrupt
• Spurious Interrupts
• Software Interrupts
• Periodic Interrupt
• Aperiodic Interrupt
• Synchronous Interrupt
• Asynchronous Interrupt

Interrupts handling more than one device:

• Polling
• Vectored Interrupts
• Interrupt Nesting
• Daisy Chain Priority

Interrupt Triggering Methods:

Interrupts are usually triggered by two ways, either by a logical signal level or an edge triggered signal.

Level Triggered Method:

Level triggered interrupts are requested by pausing the interrupt signal at its particular (either high or low) active logic level.

Level triggered interrupts always allow the generations of an interrupt whenever the level of interrupt source is asserted.

Edge Triggered Method:

In Edge trigged interrupt interrupts are generated if it can detect an asserting edge of the interrupt source. The edge may be detected when the interrupt source level changes, furthermore, it can be detected by the continuous sampling and detection of asserted levels when the previous sample was de-asserted.

Basic operations of interrupts include:

1. CPU issues a read command.
2. Whilst the CPU processes, the input/output module get the data from the peripheral.
3. Input/output request data.
4. The CPU will request the data,
5. Input/output transfers data.

References:

1. https://static.lwn.net/images/pdf/LDD3/ch10.pdf
2. https://web.archive.org/web/20160426144654/http://www.sltf.com/articles/pein/pein9505.htm
3. http://www.tldp.org/LDP/lkmpg/2.6/html/x1256.html
4. geeksforgeeks.org/interrupts/
5. https://techterms.com/definition/jitter
6. https://techterms.com/definition/interrupt
7. http://inputoutput5822.weebly.com/interrupt-driven-io.html
8. https://www.garystringham.com/level-triggered-vs-edge-triggered-interrupts/
9. https://en.wikipedia.org/wiki/Pulse_(signal_processing)
10. https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/
11. https://www.geeksforgeeks.org/interrupts/
12. https://en.wikipedia.org/wiki/Interrupt_handler
13. https://medium.com/@waliamrinal/what-are-interrupts-in-computer-organisation-e23a223b3f75#:~:text=In%20computer%20architecture%2C%20an%20interrupt,event%20that%20needs%20immediate%20attention
14. https://en.wikipedia.org/wiki/Polling_(computer_science)